/**
  ******************************************************************************
  * @file    mm_misc_reg.h
  * @version V1.0
  * @date    2021-07-12
  * @brief   This file is the description of.IP register
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __MM_MISC_REG_H__
#define __MM_MISC_REG_H__

#include "bl808.h"

/* 0x0 : CPU0_Boot */
#define MM_MISC_CPU0_BOOT_OFFSET   (0x0)
#define MM_MISC_REG_CPU0_RVBA      MM_MISC_REG_CPU0_RVBA
#define MM_MISC_REG_CPU0_RVBA_POS  (0U)
#define MM_MISC_REG_CPU0_RVBA_LEN  (32U)
#define MM_MISC_REG_CPU0_RVBA_MSK  (((1U << MM_MISC_REG_CPU0_RVBA_LEN) - 1) << MM_MISC_REG_CPU0_RVBA_POS)
#define MM_MISC_REG_CPU0_RVBA_UMSK (~(((1U << MM_MISC_REG_CPU0_RVBA_LEN) - 1) << MM_MISC_REG_CPU0_RVBA_POS))

/* 0x8 : CPU_cfg */
#define MM_MISC_CPU_CFG_OFFSET         (0x8)
#define MM_MISC_REG_CPU0_APB_BASE      MM_MISC_REG_CPU0_APB_BASE
#define MM_MISC_REG_CPU0_APB_BASE_POS  (0U)
#define MM_MISC_REG_CPU0_APB_BASE_LEN  (13U)
#define MM_MISC_REG_CPU0_APB_BASE_MSK  (((1U << MM_MISC_REG_CPU0_APB_BASE_LEN) - 1) << MM_MISC_REG_CPU0_APB_BASE_POS)
#define MM_MISC_REG_CPU0_APB_BASE_UMSK (~(((1U << MM_MISC_REG_CPU0_APB_BASE_LEN) - 1) << MM_MISC_REG_CPU0_APB_BASE_POS))
#define MM_MISC_CPU0_NDM_RSTN_EN       MM_MISC_CPU0_NDM_RSTN_EN
#define MM_MISC_CPU0_NDM_RSTN_EN_POS   (28U)
#define MM_MISC_CPU0_NDM_RSTN_EN_LEN   (1U)
#define MM_MISC_CPU0_NDM_RSTN_EN_MSK   (((1U << MM_MISC_CPU0_NDM_RSTN_EN_LEN) - 1) << MM_MISC_CPU0_NDM_RSTN_EN_POS)
#define MM_MISC_CPU0_NDM_RSTN_EN_UMSK  (~(((1U << MM_MISC_CPU0_NDM_RSTN_EN_LEN) - 1) << MM_MISC_CPU0_NDM_RSTN_EN_POS))
#define MM_MISC_CPU0_HART_RSTN_EN      MM_MISC_CPU0_HART_RSTN_EN
#define MM_MISC_CPU0_HART_RSTN_EN_POS  (29U)
#define MM_MISC_CPU0_HART_RSTN_EN_LEN  (1U)
#define MM_MISC_CPU0_HART_RSTN_EN_MSK  (((1U << MM_MISC_CPU0_HART_RSTN_EN_LEN) - 1) << MM_MISC_CPU0_HART_RSTN_EN_POS)
#define MM_MISC_CPU0_HART_RSTN_EN_UMSK (~(((1U << MM_MISC_CPU0_HART_RSTN_EN_LEN) - 1) << MM_MISC_CPU0_HART_RSTN_EN_POS))

/* 0xC : CPU_sts1 */
#define MM_MISC_CPU_STS1_OFFSET           (0xC)
#define MM_MISC_CPU0_LPMD_B               MM_MISC_CPU0_LPMD_B
#define MM_MISC_CPU0_LPMD_B_POS           (4U)
#define MM_MISC_CPU0_LPMD_B_LEN           (2U)
#define MM_MISC_CPU0_LPMD_B_MSK           (((1U << MM_MISC_CPU0_LPMD_B_LEN) - 1) << MM_MISC_CPU0_LPMD_B_POS)
#define MM_MISC_CPU0_LPMD_B_UMSK          (~(((1U << MM_MISC_CPU0_LPMD_B_LEN) - 1) << MM_MISC_CPU0_LPMD_B_POS))
#define MM_MISC_CPU0_RETIRE_PC_39_32      MM_MISC_CPU0_RETIRE_PC_39_32
#define MM_MISC_CPU0_RETIRE_PC_39_32_POS  (16U)
#define MM_MISC_CPU0_RETIRE_PC_39_32_LEN  (8U)
#define MM_MISC_CPU0_RETIRE_PC_39_32_MSK  (((1U << MM_MISC_CPU0_RETIRE_PC_39_32_LEN) - 1) << MM_MISC_CPU0_RETIRE_PC_39_32_POS)
#define MM_MISC_CPU0_RETIRE_PC_39_32_UMSK (~(((1U << MM_MISC_CPU0_RETIRE_PC_39_32_LEN) - 1) << MM_MISC_CPU0_RETIRE_PC_39_32_POS))
#define MM_MISC_CPU0_RETIRE               MM_MISC_CPU0_RETIRE
#define MM_MISC_CPU0_RETIRE_POS           (24U)
#define MM_MISC_CPU0_RETIRE_LEN           (1U)
#define MM_MISC_CPU0_RETIRE_MSK           (((1U << MM_MISC_CPU0_RETIRE_LEN) - 1) << MM_MISC_CPU0_RETIRE_POS)
#define MM_MISC_CPU0_RETIRE_UMSK          (~(((1U << MM_MISC_CPU0_RETIRE_LEN) - 1) << MM_MISC_CPU0_RETIRE_POS))
#define MM_MISC_CPU0_PAD_HALTED           MM_MISC_CPU0_PAD_HALTED
#define MM_MISC_CPU0_PAD_HALTED_POS       (25U)
#define MM_MISC_CPU0_PAD_HALTED_LEN       (1U)
#define MM_MISC_CPU0_PAD_HALTED_MSK       (((1U << MM_MISC_CPU0_PAD_HALTED_LEN) - 1) << MM_MISC_CPU0_PAD_HALTED_POS)
#define MM_MISC_CPU0_PAD_HALTED_UMSK      (~(((1U << MM_MISC_CPU0_PAD_HALTED_LEN) - 1) << MM_MISC_CPU0_PAD_HALTED_POS))
#define MM_MISC_CPU0_NDM_RSTN_REQ         MM_MISC_CPU0_NDM_RSTN_REQ
#define MM_MISC_CPU0_NDM_RSTN_REQ_POS     (28U)
#define MM_MISC_CPU0_NDM_RSTN_REQ_LEN     (1U)
#define MM_MISC_CPU0_NDM_RSTN_REQ_MSK     (((1U << MM_MISC_CPU0_NDM_RSTN_REQ_LEN) - 1) << MM_MISC_CPU0_NDM_RSTN_REQ_POS)
#define MM_MISC_CPU0_NDM_RSTN_REQ_UMSK    (~(((1U << MM_MISC_CPU0_NDM_RSTN_REQ_LEN) - 1) << MM_MISC_CPU0_NDM_RSTN_REQ_POS))
#define MM_MISC_CPU0_HART_RSTN_REQ        MM_MISC_CPU0_HART_RSTN_REQ
#define MM_MISC_CPU0_HART_RSTN_REQ_POS    (29U)
#define MM_MISC_CPU0_HART_RSTN_REQ_LEN    (1U)
#define MM_MISC_CPU0_HART_RSTN_REQ_MSK    (((1U << MM_MISC_CPU0_HART_RSTN_REQ_LEN) - 1) << MM_MISC_CPU0_HART_RSTN_REQ_POS)
#define MM_MISC_CPU0_HART_RSTN_REQ_UMSK   (~(((1U << MM_MISC_CPU0_HART_RSTN_REQ_LEN) - 1) << MM_MISC_CPU0_HART_RSTN_REQ_POS))

/* 0x10 : CPU_sts2 */
#define MM_MISC_CPU_STS2_OFFSET          (0x10)
#define MM_MISC_CPU0_RETIRE_PC_31_0      MM_MISC_CPU0_RETIRE_PC_31_0
#define MM_MISC_CPU0_RETIRE_PC_31_0_POS  (0U)
#define MM_MISC_CPU0_RETIRE_PC_31_0_LEN  (32U)
#define MM_MISC_CPU0_RETIRE_PC_31_0_MSK  (((1U << MM_MISC_CPU0_RETIRE_PC_31_0_LEN) - 1) << MM_MISC_CPU0_RETIRE_PC_31_0_POS)
#define MM_MISC_CPU0_RETIRE_PC_31_0_UMSK (~(((1U << MM_MISC_CPU0_RETIRE_PC_31_0_LEN) - 1) << MM_MISC_CPU0_RETIRE_PC_31_0_POS))

/* 0x18 : CPU_RTC */
#define MM_MISC_CPU_RTC_OFFSET    (0x18)
#define MM_MISC_C906_RTC_DIV      MM_MISC_C906_RTC_DIV
#define MM_MISC_C906_RTC_DIV_POS  (0U)
#define MM_MISC_C906_RTC_DIV_LEN  (10U)
#define MM_MISC_C906_RTC_DIV_MSK  (((1U << MM_MISC_C906_RTC_DIV_LEN) - 1) << MM_MISC_C906_RTC_DIV_POS)
#define MM_MISC_C906_RTC_DIV_UMSK (~(((1U << MM_MISC_C906_RTC_DIV_LEN) - 1) << MM_MISC_C906_RTC_DIV_POS))
#define MM_MISC_C906_RTC_RST      MM_MISC_C906_RTC_RST
#define MM_MISC_C906_RTC_RST_POS  (30U)
#define MM_MISC_C906_RTC_RST_LEN  (1U)
#define MM_MISC_C906_RTC_RST_MSK  (((1U << MM_MISC_C906_RTC_RST_LEN) - 1) << MM_MISC_C906_RTC_RST_POS)
#define MM_MISC_C906_RTC_RST_UMSK (~(((1U << MM_MISC_C906_RTC_RST_LEN) - 1) << MM_MISC_C906_RTC_RST_POS))
#define MM_MISC_C906_RTC_EN       MM_MISC_C906_RTC_EN
#define MM_MISC_C906_RTC_EN_POS   (31U)
#define MM_MISC_C906_RTC_EN_LEN   (1U)
#define MM_MISC_C906_RTC_EN_MSK   (((1U << MM_MISC_C906_RTC_EN_LEN) - 1) << MM_MISC_C906_RTC_EN_POS)
#define MM_MISC_C906_RTC_EN_UMSK  (~(((1U << MM_MISC_C906_RTC_EN_LEN) - 1) << MM_MISC_C906_RTC_EN_POS))

/* 0x1C : tzc_mmsys_misc */
#define MM_MISC_TZC_MMSYS_MISC_OFFSET (0x1C)
#define MM_MISC_TZC_MM_CPU0_LOCK      MM_MISC_TZC_MM_CPU0_LOCK
#define MM_MISC_TZC_MM_CPU0_LOCK_POS  (0U)
#define MM_MISC_TZC_MM_CPU0_LOCK_LEN  (1U)
#define MM_MISC_TZC_MM_CPU0_LOCK_MSK  (((1U << MM_MISC_TZC_MM_CPU0_LOCK_LEN) - 1) << MM_MISC_TZC_MM_CPU0_LOCK_POS)
#define MM_MISC_TZC_MM_CPU0_LOCK_UMSK (~(((1U << MM_MISC_TZC_MM_CPU0_LOCK_LEN) - 1) << MM_MISC_TZC_MM_CPU0_LOCK_POS))
#define MM_MISC_TZC_MM_SRAM_LOCK      MM_MISC_TZC_MM_SRAM_LOCK
#define MM_MISC_TZC_MM_SRAM_LOCK_POS  (2U)
#define MM_MISC_TZC_MM_SRAM_LOCK_LEN  (1U)
#define MM_MISC_TZC_MM_SRAM_LOCK_MSK  (((1U << MM_MISC_TZC_MM_SRAM_LOCK_LEN) - 1) << MM_MISC_TZC_MM_SRAM_LOCK_POS)
#define MM_MISC_TZC_MM_SRAM_LOCK_UMSK (~(((1U << MM_MISC_TZC_MM_SRAM_LOCK_LEN) - 1) << MM_MISC_TZC_MM_SRAM_LOCK_POS))

/* 0x20 : peri_apb_ctrl */
#define MM_MISC_PERI_APB_CTRL_OFFSET         (0x20)
#define MM_MISC_REG_MMINFRA_BERR_INT_EN      MM_MISC_REG_MMINFRA_BERR_INT_EN
#define MM_MISC_REG_MMINFRA_BERR_INT_EN_POS  (0U)
#define MM_MISC_REG_MMINFRA_BERR_INT_EN_LEN  (1U)
#define MM_MISC_REG_MMINFRA_BERR_INT_EN_MSK  (((1U << MM_MISC_REG_MMINFRA_BERR_INT_EN_LEN) - 1) << MM_MISC_REG_MMINFRA_BERR_INT_EN_POS)
#define MM_MISC_REG_MMINFRA_BERR_INT_EN_UMSK (~(((1U << MM_MISC_REG_MMINFRA_BERR_INT_EN_LEN) - 1) << MM_MISC_REG_MMINFRA_BERR_INT_EN_POS))
#define MM_MISC_REG_BERR_INT_EN              MM_MISC_REG_BERR_INT_EN
#define MM_MISC_REG_BERR_INT_EN_POS          (1U)
#define MM_MISC_REG_BERR_INT_EN_LEN          (1U)
#define MM_MISC_REG_BERR_INT_EN_MSK          (((1U << MM_MISC_REG_BERR_INT_EN_LEN) - 1) << MM_MISC_REG_BERR_INT_EN_POS)
#define MM_MISC_REG_BERR_INT_EN_UMSK         (~(((1U << MM_MISC_REG_BERR_INT_EN_LEN) - 1) << MM_MISC_REG_BERR_INT_EN_POS))
#define MM_MISC_REG_CODEC_BERR_INT_EN        MM_MISC_REG_CODEC_BERR_INT_EN
#define MM_MISC_REG_CODEC_BERR_INT_EN_POS    (2U)
#define MM_MISC_REG_CODEC_BERR_INT_EN_LEN    (1U)
#define MM_MISC_REG_CODEC_BERR_INT_EN_MSK    (((1U << MM_MISC_REG_CODEC_BERR_INT_EN_LEN) - 1) << MM_MISC_REG_CODEC_BERR_INT_EN_POS)
#define MM_MISC_REG_CODEC_BERR_INT_EN_UMSK   (~(((1U << MM_MISC_REG_CODEC_BERR_INT_EN_LEN) - 1) << MM_MISC_REG_CODEC_BERR_INT_EN_POS))
#define MM_MISC_REG_MMCPU_BERR_INT_EN        MM_MISC_REG_MMCPU_BERR_INT_EN
#define MM_MISC_REG_MMCPU_BERR_INT_EN_POS    (3U)
#define MM_MISC_REG_MMCPU_BERR_INT_EN_LEN    (1U)
#define MM_MISC_REG_MMCPU_BERR_INT_EN_MSK    (((1U << MM_MISC_REG_MMCPU_BERR_INT_EN_LEN) - 1) << MM_MISC_REG_MMCPU_BERR_INT_EN_POS)
#define MM_MISC_REG_MMCPU_BERR_INT_EN_UMSK   (~(((1U << MM_MISC_REG_MMCPU_BERR_INT_EN_LEN) - 1) << MM_MISC_REG_MMCPU_BERR_INT_EN_POS))
#define MM_MISC_REG_MM_X2HS_SP_BYPASS        MM_MISC_REG_MM_X2HS_SP_BYPASS
#define MM_MISC_REG_MM_X2HS_SP_BYPASS_POS    (8U)
#define MM_MISC_REG_MM_X2HS_SP_BYPASS_LEN    (1U)
#define MM_MISC_REG_MM_X2HS_SP_BYPASS_MSK    (((1U << MM_MISC_REG_MM_X2HS_SP_BYPASS_LEN) - 1) << MM_MISC_REG_MM_X2HS_SP_BYPASS_POS)
#define MM_MISC_REG_MM_X2HS_SP_BYPASS_UMSK   (~(((1U << MM_MISC_REG_MM_X2HS_SP_BYPASS_LEN) - 1) << MM_MISC_REG_MM_X2HS_SP_BYPASS_POS))
#define MM_MISC_RG_PCLK_FORCE_ON             MM_MISC_RG_PCLK_FORCE_ON
#define MM_MISC_RG_PCLK_FORCE_ON_POS         (16U)
#define MM_MISC_RG_PCLK_FORCE_ON_LEN         (16U)
#define MM_MISC_RG_PCLK_FORCE_ON_MSK         (((1U << MM_MISC_RG_PCLK_FORCE_ON_LEN) - 1) << MM_MISC_RG_PCLK_FORCE_ON_POS)
#define MM_MISC_RG_PCLK_FORCE_ON_UMSK        (~(((1U << MM_MISC_RG_PCLK_FORCE_ON_LEN) - 1) << MM_MISC_RG_PCLK_FORCE_ON_POS))

/* 0x2C : mm_infra_qos_ctrl */
#define MM_MISC_MM_INFRA_QOS_CTRL_OFFSET  (0x2C)
#define MM_MISC_REG_MMCPU0_AWQOS          MM_MISC_REG_MMCPU0_AWQOS
#define MM_MISC_REG_MMCPU0_AWQOS_POS      (2U)
#define MM_MISC_REG_MMCPU0_AWQOS_LEN      (1U)
#define MM_MISC_REG_MMCPU0_AWQOS_MSK      (((1U << MM_MISC_REG_MMCPU0_AWQOS_LEN) - 1) << MM_MISC_REG_MMCPU0_AWQOS_POS)
#define MM_MISC_REG_MMCPU0_AWQOS_UMSK     (~(((1U << MM_MISC_REG_MMCPU0_AWQOS_LEN) - 1) << MM_MISC_REG_MMCPU0_AWQOS_POS))
#define MM_MISC_REG_MMCPU0_ARQOS          MM_MISC_REG_MMCPU0_ARQOS
#define MM_MISC_REG_MMCPU0_ARQOS_POS      (3U)
#define MM_MISC_REG_MMCPU0_ARQOS_LEN      (1U)
#define MM_MISC_REG_MMCPU0_ARQOS_MSK      (((1U << MM_MISC_REG_MMCPU0_ARQOS_LEN) - 1) << MM_MISC_REG_MMCPU0_ARQOS_POS)
#define MM_MISC_REG_MMCPU0_ARQOS_UMSK     (~(((1U << MM_MISC_REG_MMCPU0_ARQOS_LEN) - 1) << MM_MISC_REG_MMCPU0_ARQOS_POS))
#define MM_MISC_REG_H_WTHRE_MM2CONN       MM_MISC_REG_H_WTHRE_MM2CONN
#define MM_MISC_REG_H_WTHRE_MM2CONN_POS   (16U)
#define MM_MISC_REG_H_WTHRE_MM2CONN_LEN   (2U)
#define MM_MISC_REG_H_WTHRE_MM2CONN_MSK   (((1U << MM_MISC_REG_H_WTHRE_MM2CONN_LEN) - 1) << MM_MISC_REG_H_WTHRE_MM2CONN_POS)
#define MM_MISC_REG_H_WTHRE_MM2CONN_UMSK  (~(((1U << MM_MISC_REG_H_WTHRE_MM2CONN_LEN) - 1) << MM_MISC_REG_H_WTHRE_MM2CONN_POS))
#define MM_MISC_REG_H_WTHRE_CONN2MM       MM_MISC_REG_H_WTHRE_CONN2MM
#define MM_MISC_REG_H_WTHRE_CONN2MM_POS   (18U)
#define MM_MISC_REG_H_WTHRE_CONN2MM_LEN   (2U)
#define MM_MISC_REG_H_WTHRE_CONN2MM_MSK   (((1U << MM_MISC_REG_H_WTHRE_CONN2MM_LEN) - 1) << MM_MISC_REG_H_WTHRE_CONN2MM_POS)
#define MM_MISC_REG_H_WTHRE_CONN2MM_UMSK  (~(((1U << MM_MISC_REG_H_WTHRE_CONN2MM_LEN) - 1) << MM_MISC_REG_H_WTHRE_CONN2MM_POS))
#define MM_MISC_REG_X_WTHRE_MMHW2PA       MM_MISC_REG_X_WTHRE_MMHW2PA
#define MM_MISC_REG_X_WTHRE_MMHW2PA_POS   (20U)
#define MM_MISC_REG_X_WTHRE_MMHW2PA_LEN   (2U)
#define MM_MISC_REG_X_WTHRE_MMHW2PA_MSK   (((1U << MM_MISC_REG_X_WTHRE_MMHW2PA_LEN) - 1) << MM_MISC_REG_X_WTHRE_MMHW2PA_POS)
#define MM_MISC_REG_X_WTHRE_MMHW2PA_UMSK  (~(((1U << MM_MISC_REG_X_WTHRE_MMHW2PA_LEN) - 1) << MM_MISC_REG_X_WTHRE_MMHW2PA_POS))
#define MM_MISC_REG_X_WTHRE_MMHW2EXT      MM_MISC_REG_X_WTHRE_MMHW2EXT
#define MM_MISC_REG_X_WTHRE_MMHW2EXT_POS  (22U)
#define MM_MISC_REG_X_WTHRE_MMHW2EXT_LEN  (2U)
#define MM_MISC_REG_X_WTHRE_MMHW2EXT_MSK  (((1U << MM_MISC_REG_X_WTHRE_MMHW2EXT_LEN) - 1) << MM_MISC_REG_X_WTHRE_MMHW2EXT_POS)
#define MM_MISC_REG_X_WTHRE_MMHW2EXT_UMSK (~(((1U << MM_MISC_REG_X_WTHRE_MMHW2EXT_LEN) - 1) << MM_MISC_REG_X_WTHRE_MMHW2EXT_POS))
#define MM_MISC_REG_X_WTHRE_PUHS          MM_MISC_REG_X_WTHRE_PUHS
#define MM_MISC_REG_X_WTHRE_PUHS_POS      (24U)
#define MM_MISC_REG_X_WTHRE_PUHS_LEN      (2U)
#define MM_MISC_REG_X_WTHRE_PUHS_MSK      (((1U << MM_MISC_REG_X_WTHRE_PUHS_LEN) - 1) << MM_MISC_REG_X_WTHRE_PUHS_POS)
#define MM_MISC_REG_X_WTHRE_PUHS_UMSK     (~(((1U << MM_MISC_REG_X_WTHRE_PUHS_LEN) - 1) << MM_MISC_REG_X_WTHRE_PUHS_POS))

/* 0x40 : dma_clk_ctrl */
#define MM_MISC_DMA_CLK_CTRL_OFFSET (0x40)
#define MM_MISC_DMA_CLK_EN          MM_MISC_DMA_CLK_EN
#define MM_MISC_DMA_CLK_EN_POS      (0U)
#define MM_MISC_DMA_CLK_EN_LEN      (8U)
#define MM_MISC_DMA_CLK_EN_MSK      (((1U << MM_MISC_DMA_CLK_EN_LEN) - 1) << MM_MISC_DMA_CLK_EN_POS)
#define MM_MISC_DMA_CLK_EN_UMSK     (~(((1U << MM_MISC_DMA_CLK_EN_LEN) - 1) << MM_MISC_DMA_CLK_EN_POS))

/* 0x50 : vram_ctrl */
#define MM_MISC_VRAM_CTRL_OFFSET       (0x50)
#define MM_MISC_REG_SYSRAM_SET         MM_MISC_REG_SYSRAM_SET
#define MM_MISC_REG_SYSRAM_SET_POS     (0U)
#define MM_MISC_REG_SYSRAM_SET_LEN     (1U)
#define MM_MISC_REG_SYSRAM_SET_MSK     (((1U << MM_MISC_REG_SYSRAM_SET_LEN) - 1) << MM_MISC_REG_SYSRAM_SET_POS)
#define MM_MISC_REG_SYSRAM_SET_UMSK    (~(((1U << MM_MISC_REG_SYSRAM_SET_LEN) - 1) << MM_MISC_REG_SYSRAM_SET_POS))
#define MM_MISC_REG_H2PF_SRAM_REL      MM_MISC_REG_H2PF_SRAM_REL
#define MM_MISC_REG_H2PF_SRAM_REL_POS  (1U)
#define MM_MISC_REG_H2PF_SRAM_REL_LEN  (2U)
#define MM_MISC_REG_H2PF_SRAM_REL_MSK  (((1U << MM_MISC_REG_H2PF_SRAM_REL_LEN) - 1) << MM_MISC_REG_H2PF_SRAM_REL_POS)
#define MM_MISC_REG_H2PF_SRAM_REL_UMSK (~(((1U << MM_MISC_REG_H2PF_SRAM_REL_LEN) - 1) << MM_MISC_REG_H2PF_SRAM_REL_POS))
#define MM_MISC_REG_VRAM_SRAM_REL      MM_MISC_REG_VRAM_SRAM_REL
#define MM_MISC_REG_VRAM_SRAM_REL_POS  (4U)
#define MM_MISC_REG_VRAM_SRAM_REL_LEN  (1U)
#define MM_MISC_REG_VRAM_SRAM_REL_MSK  (((1U << MM_MISC_REG_VRAM_SRAM_REL_LEN) - 1) << MM_MISC_REG_VRAM_SRAM_REL_POS)
#define MM_MISC_REG_VRAM_SRAM_REL_UMSK (~(((1U << MM_MISC_REG_VRAM_SRAM_REL_LEN) - 1) << MM_MISC_REG_VRAM_SRAM_REL_POS))
#define MM_MISC_REG_SUB_SRAM_REL       MM_MISC_REG_SUB_SRAM_REL
#define MM_MISC_REG_SUB_SRAM_REL_POS   (6U)
#define MM_MISC_REG_SUB_SRAM_REL_LEN   (1U)
#define MM_MISC_REG_SUB_SRAM_REL_MSK   (((1U << MM_MISC_REG_SUB_SRAM_REL_LEN) - 1) << MM_MISC_REG_SUB_SRAM_REL_POS)
#define MM_MISC_REG_SUB_SRAM_REL_UMSK  (~(((1U << MM_MISC_REG_SUB_SRAM_REL_LEN) - 1) << MM_MISC_REG_SUB_SRAM_REL_POS))
#define MM_MISC_REG_BLAI_SRAM_REL      MM_MISC_REG_BLAI_SRAM_REL
#define MM_MISC_REG_BLAI_SRAM_REL_POS  (7U)
#define MM_MISC_REG_BLAI_SRAM_REL_LEN  (1U)
#define MM_MISC_REG_BLAI_SRAM_REL_MSK  (((1U << MM_MISC_REG_BLAI_SRAM_REL_LEN) - 1) << MM_MISC_REG_BLAI_SRAM_REL_POS)
#define MM_MISC_REG_BLAI_SRAM_REL_UMSK (~(((1U << MM_MISC_REG_BLAI_SRAM_REL_LEN) - 1) << MM_MISC_REG_BLAI_SRAM_REL_POS))
#define MM_MISC_REG_H2PF_SRAM_SEL      MM_MISC_REG_H2PF_SRAM_SEL
#define MM_MISC_REG_H2PF_SRAM_SEL_POS  (8U)
#define MM_MISC_REG_H2PF_SRAM_SEL_LEN  (3U)
#define MM_MISC_REG_H2PF_SRAM_SEL_MSK  (((1U << MM_MISC_REG_H2PF_SRAM_SEL_LEN) - 1) << MM_MISC_REG_H2PF_SRAM_SEL_POS)
#define MM_MISC_REG_H2PF_SRAM_SEL_UMSK (~(((1U << MM_MISC_REG_H2PF_SRAM_SEL_LEN) - 1) << MM_MISC_REG_H2PF_SRAM_SEL_POS))
#define MM_MISC_REG_VRAM_SRAM_SEL      MM_MISC_REG_VRAM_SRAM_SEL
#define MM_MISC_REG_VRAM_SRAM_SEL_POS  (12U)
#define MM_MISC_REG_VRAM_SRAM_SEL_LEN  (1U)
#define MM_MISC_REG_VRAM_SRAM_SEL_MSK  (((1U << MM_MISC_REG_VRAM_SRAM_SEL_LEN) - 1) << MM_MISC_REG_VRAM_SRAM_SEL_POS)
#define MM_MISC_REG_VRAM_SRAM_SEL_UMSK (~(((1U << MM_MISC_REG_VRAM_SRAM_SEL_LEN) - 1) << MM_MISC_REG_VRAM_SRAM_SEL_POS))
#define MM_MISC_REG_SUB_SRAM_SEL       MM_MISC_REG_SUB_SRAM_SEL
#define MM_MISC_REG_SUB_SRAM_SEL_POS   (14U)
#define MM_MISC_REG_SUB_SRAM_SEL_LEN   (1U)
#define MM_MISC_REG_SUB_SRAM_SEL_MSK   (((1U << MM_MISC_REG_SUB_SRAM_SEL_LEN) - 1) << MM_MISC_REG_SUB_SRAM_SEL_POS)
#define MM_MISC_REG_SUB_SRAM_SEL_UMSK  (~(((1U << MM_MISC_REG_SUB_SRAM_SEL_LEN) - 1) << MM_MISC_REG_SUB_SRAM_SEL_POS))
#define MM_MISC_REG_BLAI_SRAM_SEL      MM_MISC_REG_BLAI_SRAM_SEL
#define MM_MISC_REG_BLAI_SRAM_SEL_POS  (15U)
#define MM_MISC_REG_BLAI_SRAM_SEL_LEN  (1U)
#define MM_MISC_REG_BLAI_SRAM_SEL_MSK  (((1U << MM_MISC_REG_BLAI_SRAM_SEL_LEN) - 1) << MM_MISC_REG_BLAI_SRAM_SEL_POS)
#define MM_MISC_REG_BLAI_SRAM_SEL_UMSK (~(((1U << MM_MISC_REG_BLAI_SRAM_SEL_LEN) - 1) << MM_MISC_REG_BLAI_SRAM_SEL_POS))

/* 0x60 : sram_parm */
#define MM_MISC_SRAM_PARM_OFFSET           (0x60)
#define MM_MISC_REG_SRAM_CPU_RAM_DVS       MM_MISC_REG_SRAM_CPU_RAM_DVS
#define MM_MISC_REG_SRAM_CPU_RAM_DVS_POS   (0U)
#define MM_MISC_REG_SRAM_CPU_RAM_DVS_LEN   (4U)
#define MM_MISC_REG_SRAM_CPU_RAM_DVS_MSK   (((1U << MM_MISC_REG_SRAM_CPU_RAM_DVS_LEN) - 1) << MM_MISC_REG_SRAM_CPU_RAM_DVS_POS)
#define MM_MISC_REG_SRAM_CPU_RAM_DVS_UMSK  (~(((1U << MM_MISC_REG_SRAM_CPU_RAM_DVS_LEN) - 1) << MM_MISC_REG_SRAM_CPU_RAM_DVS_POS))
#define MM_MISC_REG_SRAM_CPU_RAM_DVSE      MM_MISC_REG_SRAM_CPU_RAM_DVSE
#define MM_MISC_REG_SRAM_CPU_RAM_DVSE_POS  (4U)
#define MM_MISC_REG_SRAM_CPU_RAM_DVSE_LEN  (1U)
#define MM_MISC_REG_SRAM_CPU_RAM_DVSE_MSK  (((1U << MM_MISC_REG_SRAM_CPU_RAM_DVSE_LEN) - 1) << MM_MISC_REG_SRAM_CPU_RAM_DVSE_POS)
#define MM_MISC_REG_SRAM_CPU_RAM_DVSE_UMSK (~(((1U << MM_MISC_REG_SRAM_CPU_RAM_DVSE_LEN) - 1) << MM_MISC_REG_SRAM_CPU_RAM_DVSE_POS))
#define MM_MISC_REG_SRAM_CPU_RAM_NAP       MM_MISC_REG_SRAM_CPU_RAM_NAP
#define MM_MISC_REG_SRAM_CPU_RAM_NAP_POS   (5U)
#define MM_MISC_REG_SRAM_CPU_RAM_NAP_LEN   (1U)
#define MM_MISC_REG_SRAM_CPU_RAM_NAP_MSK   (((1U << MM_MISC_REG_SRAM_CPU_RAM_NAP_LEN) - 1) << MM_MISC_REG_SRAM_CPU_RAM_NAP_POS)
#define MM_MISC_REG_SRAM_CPU_RAM_NAP_UMSK  (~(((1U << MM_MISC_REG_SRAM_CPU_RAM_NAP_LEN) - 1) << MM_MISC_REG_SRAM_CPU_RAM_NAP_POS))
#define MM_MISC_REG_SRAM_L2RAM_DVS         MM_MISC_REG_SRAM_L2RAM_DVS
#define MM_MISC_REG_SRAM_L2RAM_DVS_POS     (8U)
#define MM_MISC_REG_SRAM_L2RAM_DVS_LEN     (4U)
#define MM_MISC_REG_SRAM_L2RAM_DVS_MSK     (((1U << MM_MISC_REG_SRAM_L2RAM_DVS_LEN) - 1) << MM_MISC_REG_SRAM_L2RAM_DVS_POS)
#define MM_MISC_REG_SRAM_L2RAM_DVS_UMSK    (~(((1U << MM_MISC_REG_SRAM_L2RAM_DVS_LEN) - 1) << MM_MISC_REG_SRAM_L2RAM_DVS_POS))
#define MM_MISC_REG_SRAM_L2RAM_DVSE        MM_MISC_REG_SRAM_L2RAM_DVSE
#define MM_MISC_REG_SRAM_L2RAM_DVSE_POS    (12U)
#define MM_MISC_REG_SRAM_L2RAM_DVSE_LEN    (1U)
#define MM_MISC_REG_SRAM_L2RAM_DVSE_MSK    (((1U << MM_MISC_REG_SRAM_L2RAM_DVSE_LEN) - 1) << MM_MISC_REG_SRAM_L2RAM_DVSE_POS)
#define MM_MISC_REG_SRAM_L2RAM_DVSE_UMSK   (~(((1U << MM_MISC_REG_SRAM_L2RAM_DVSE_LEN) - 1) << MM_MISC_REG_SRAM_L2RAM_DVSE_POS))
#define MM_MISC_REG_SRAM_L2RAM_NAP         MM_MISC_REG_SRAM_L2RAM_NAP
#define MM_MISC_REG_SRAM_L2RAM_NAP_POS     (13U)
#define MM_MISC_REG_SRAM_L2RAM_NAP_LEN     (1U)
#define MM_MISC_REG_SRAM_L2RAM_NAP_MSK     (((1U << MM_MISC_REG_SRAM_L2RAM_NAP_LEN) - 1) << MM_MISC_REG_SRAM_L2RAM_NAP_POS)
#define MM_MISC_REG_SRAM_L2RAM_NAP_UMSK    (~(((1U << MM_MISC_REG_SRAM_L2RAM_NAP_LEN) - 1) << MM_MISC_REG_SRAM_L2RAM_NAP_POS))
#define MM_MISC_REG_SRAM_CDC_RAM_DVS       MM_MISC_REG_SRAM_CDC_RAM_DVS
#define MM_MISC_REG_SRAM_CDC_RAM_DVS_POS   (16U)
#define MM_MISC_REG_SRAM_CDC_RAM_DVS_LEN   (4U)
#define MM_MISC_REG_SRAM_CDC_RAM_DVS_MSK   (((1U << MM_MISC_REG_SRAM_CDC_RAM_DVS_LEN) - 1) << MM_MISC_REG_SRAM_CDC_RAM_DVS_POS)
#define MM_MISC_REG_SRAM_CDC_RAM_DVS_UMSK  (~(((1U << MM_MISC_REG_SRAM_CDC_RAM_DVS_LEN) - 1) << MM_MISC_REG_SRAM_CDC_RAM_DVS_POS))
#define MM_MISC_REG_SRAM_CDC_RAM_DVSE      MM_MISC_REG_SRAM_CDC_RAM_DVSE
#define MM_MISC_REG_SRAM_CDC_RAM_DVSE_POS  (20U)
#define MM_MISC_REG_SRAM_CDC_RAM_DVSE_LEN  (1U)
#define MM_MISC_REG_SRAM_CDC_RAM_DVSE_MSK  (((1U << MM_MISC_REG_SRAM_CDC_RAM_DVSE_LEN) - 1) << MM_MISC_REG_SRAM_CDC_RAM_DVSE_POS)
#define MM_MISC_REG_SRAM_CDC_RAM_DVSE_UMSK (~(((1U << MM_MISC_REG_SRAM_CDC_RAM_DVSE_LEN) - 1) << MM_MISC_REG_SRAM_CDC_RAM_DVSE_POS))
#define MM_MISC_REG_SRAM_CDC_RAM_NAP       MM_MISC_REG_SRAM_CDC_RAM_NAP
#define MM_MISC_REG_SRAM_CDC_RAM_NAP_POS   (21U)
#define MM_MISC_REG_SRAM_CDC_RAM_NAP_LEN   (1U)
#define MM_MISC_REG_SRAM_CDC_RAM_NAP_MSK   (((1U << MM_MISC_REG_SRAM_CDC_RAM_NAP_LEN) - 1) << MM_MISC_REG_SRAM_CDC_RAM_NAP_POS)
#define MM_MISC_REG_SRAM_CDC_RAM_NAP_UMSK  (~(((1U << MM_MISC_REG_SRAM_CDC_RAM_NAP_LEN) - 1) << MM_MISC_REG_SRAM_CDC_RAM_NAP_POS))
#define MM_MISC_REG_SRAM_SUB_RAM_DVS       MM_MISC_REG_SRAM_SUB_RAM_DVS
#define MM_MISC_REG_SRAM_SUB_RAM_DVS_POS   (24U)
#define MM_MISC_REG_SRAM_SUB_RAM_DVS_LEN   (4U)
#define MM_MISC_REG_SRAM_SUB_RAM_DVS_MSK   (((1U << MM_MISC_REG_SRAM_SUB_RAM_DVS_LEN) - 1) << MM_MISC_REG_SRAM_SUB_RAM_DVS_POS)
#define MM_MISC_REG_SRAM_SUB_RAM_DVS_UMSK  (~(((1U << MM_MISC_REG_SRAM_SUB_RAM_DVS_LEN) - 1) << MM_MISC_REG_SRAM_SUB_RAM_DVS_POS))
#define MM_MISC_REG_SRAM_SUB_RAM_DVSE      MM_MISC_REG_SRAM_SUB_RAM_DVSE
#define MM_MISC_REG_SRAM_SUB_RAM_DVSE_POS  (28U)
#define MM_MISC_REG_SRAM_SUB_RAM_DVSE_LEN  (1U)
#define MM_MISC_REG_SRAM_SUB_RAM_DVSE_MSK  (((1U << MM_MISC_REG_SRAM_SUB_RAM_DVSE_LEN) - 1) << MM_MISC_REG_SRAM_SUB_RAM_DVSE_POS)
#define MM_MISC_REG_SRAM_SUB_RAM_DVSE_UMSK (~(((1U << MM_MISC_REG_SRAM_SUB_RAM_DVSE_LEN) - 1) << MM_MISC_REG_SRAM_SUB_RAM_DVSE_POS))
#define MM_MISC_REG_SRAM_SUB_RAM_NAP       MM_MISC_REG_SRAM_SUB_RAM_NAP
#define MM_MISC_REG_SRAM_SUB_RAM_NAP_POS   (29U)
#define MM_MISC_REG_SRAM_SUB_RAM_NAP_LEN   (1U)
#define MM_MISC_REG_SRAM_SUB_RAM_NAP_MSK   (((1U << MM_MISC_REG_SRAM_SUB_RAM_NAP_LEN) - 1) << MM_MISC_REG_SRAM_SUB_RAM_NAP_POS)
#define MM_MISC_REG_SRAM_SUB_RAM_NAP_UMSK  (~(((1U << MM_MISC_REG_SRAM_SUB_RAM_NAP_LEN) - 1) << MM_MISC_REG_SRAM_SUB_RAM_NAP_POS))

/* 0xA0 : MM_INT_STA0 */
#define MM_MISC_MM_INT_STA0_OFFSET (0xA0)
#define MM_MISC_MM_INT_STA0        MM_MISC_MM_INT_STA0
#define MM_MISC_MM_INT_STA0_POS    (0U)
#define MM_MISC_MM_INT_STA0_LEN    (32U)
#define MM_MISC_MM_INT_STA0_MSK    (((1U << MM_MISC_MM_INT_STA0_LEN) - 1) << MM_MISC_MM_INT_STA0_POS)
#define MM_MISC_MM_INT_STA0_UMSK   (~(((1U << MM_MISC_MM_INT_STA0_LEN) - 1) << MM_MISC_MM_INT_STA0_POS))

/* 0xA4 : MM_INT_MASK0 */
#define MM_MISC_MM_INT_MASK0_OFFSET (0xA4)
#define MM_MISC_MM_INT_MASK0        MM_MISC_MM_INT_MASK0
#define MM_MISC_MM_INT_MASK0_POS    (0U)
#define MM_MISC_MM_INT_MASK0_LEN    (32U)
#define MM_MISC_MM_INT_MASK0_MSK    (((1U << MM_MISC_MM_INT_MASK0_LEN) - 1) << MM_MISC_MM_INT_MASK0_POS)
#define MM_MISC_MM_INT_MASK0_UMSK   (~(((1U << MM_MISC_MM_INT_MASK0_LEN) - 1) << MM_MISC_MM_INT_MASK0_POS))

/* 0xA8 : MM_INT_CLR_0 */
#define MM_MISC_MM_INT_CLR_0_OFFSET (0xA8)
#define MM_MISC_MM_INT_CLR0         MM_MISC_MM_INT_CLR0
#define MM_MISC_MM_INT_CLR0_POS     (0U)
#define MM_MISC_MM_INT_CLR0_LEN     (32U)
#define MM_MISC_MM_INT_CLR0_MSK     (((1U << MM_MISC_MM_INT_CLR0_LEN) - 1) << MM_MISC_MM_INT_CLR0_POS)
#define MM_MISC_MM_INT_CLR0_UMSK    (~(((1U << MM_MISC_MM_INT_CLR0_LEN) - 1) << MM_MISC_MM_INT_CLR0_POS))

/* 0xAC : MM_INT_STA1 */
#define MM_MISC_MM_INT_STA1_OFFSET (0xAC)
#define MM_MISC_MM_INT_STA1        MM_MISC_MM_INT_STA1
#define MM_MISC_MM_INT_STA1_POS    (0U)
#define MM_MISC_MM_INT_STA1_LEN    (32U)
#define MM_MISC_MM_INT_STA1_MSK    (((1U << MM_MISC_MM_INT_STA1_LEN) - 1) << MM_MISC_MM_INT_STA1_POS)
#define MM_MISC_MM_INT_STA1_UMSK   (~(((1U << MM_MISC_MM_INT_STA1_LEN) - 1) << MM_MISC_MM_INT_STA1_POS))

/* 0xB0 : MM_INT_MASK1 */
#define MM_MISC_MM_INT_MASK1_OFFSET (0xB0)
#define MM_MISC_MM_INT_MASK1        MM_MISC_MM_INT_MASK1
#define MM_MISC_MM_INT_MASK1_POS    (0U)
#define MM_MISC_MM_INT_MASK1_LEN    (32U)
#define MM_MISC_MM_INT_MASK1_MSK    (((1U << MM_MISC_MM_INT_MASK1_LEN) - 1) << MM_MISC_MM_INT_MASK1_POS)
#define MM_MISC_MM_INT_MASK1_UMSK   (~(((1U << MM_MISC_MM_INT_MASK1_LEN) - 1) << MM_MISC_MM_INT_MASK1_POS))

/* 0xB4 : MM_INT_CLR_1 */
#define MM_MISC_MM_INT_CLR_1_OFFSET (0xB4)
#define MM_MISC_MM_INT_CLR1         MM_MISC_MM_INT_CLR1
#define MM_MISC_MM_INT_CLR1_POS     (0U)
#define MM_MISC_MM_INT_CLR1_LEN     (32U)
#define MM_MISC_MM_INT_CLR1_MSK     (((1U << MM_MISC_MM_INT_CLR1_LEN) - 1) << MM_MISC_MM_INT_CLR1_POS)
#define MM_MISC_MM_INT_CLR1_UMSK    (~(((1U << MM_MISC_MM_INT_CLR1_LEN) - 1) << MM_MISC_MM_INT_CLR1_POS))

/* 0xF0 : mmsys_debug_sel */
#define MM_MISC_MMSYS_DEBUG_SEL_OFFSET (0xF0)
#define MM_MISC_MMSYS_DEBUG_SEL        MM_MISC_MMSYS_DEBUG_SEL
#define MM_MISC_MMSYS_DEBUG_SEL_POS    (0U)
#define MM_MISC_MMSYS_DEBUG_SEL_LEN    (4U)
#define MM_MISC_MMSYS_DEBUG_SEL_MSK    (((1U << MM_MISC_MMSYS_DEBUG_SEL_LEN) - 1) << MM_MISC_MMSYS_DEBUG_SEL_POS)
#define MM_MISC_MMSYS_DEBUG_SEL_UMSK   (~(((1U << MM_MISC_MMSYS_DEBUG_SEL_LEN) - 1) << MM_MISC_MMSYS_DEBUG_SEL_POS))

/* 0xFC : mmsys_misc_dummy */
#define MM_MISC_MMSYS_MISC_DUMMY_OFFSET  (0xFC)
#define MM_MISC_PIR_CTRL_O               MM_MISC_PIR_CTRL_O
#define MM_MISC_PIR_CTRL_O_POS           (0U)
#define MM_MISC_PIR_CTRL_O_LEN           (1U)
#define MM_MISC_PIR_CTRL_O_MSK           (((1U << MM_MISC_PIR_CTRL_O_LEN) - 1) << MM_MISC_PIR_CTRL_O_POS)
#define MM_MISC_PIR_CTRL_O_UMSK          (~(((1U << MM_MISC_PIR_CTRL_O_LEN) - 1) << MM_MISC_PIR_CTRL_O_POS))
#define MM_MISC_LIGHT_SENSOR_CTRL_O      MM_MISC_LIGHT_SENSOR_CTRL_O
#define MM_MISC_LIGHT_SENSOR_CTRL_O_POS  (1U)
#define MM_MISC_LIGHT_SENSOR_CTRL_O_LEN  (1U)
#define MM_MISC_LIGHT_SENSOR_CTRL_O_MSK  (((1U << MM_MISC_LIGHT_SENSOR_CTRL_O_LEN) - 1) << MM_MISC_LIGHT_SENSOR_CTRL_O_POS)
#define MM_MISC_LIGHT_SENSOR_CTRL_O_UMSK (~(((1U << MM_MISC_LIGHT_SENSOR_CTRL_O_LEN) - 1) << MM_MISC_LIGHT_SENSOR_CTRL_O_POS))
#define MM_MISC_IR_CUT_CTRL_O            MM_MISC_IR_CUT_CTRL_O
#define MM_MISC_IR_CUT_CTRL_O_POS        (2U)
#define MM_MISC_IR_CUT_CTRL_O_LEN        (1U)
#define MM_MISC_IR_CUT_CTRL_O_MSK        (((1U << MM_MISC_IR_CUT_CTRL_O_LEN) - 1) << MM_MISC_IR_CUT_CTRL_O_POS)
#define MM_MISC_IR_CUT_CTRL_O_UMSK       (~(((1U << MM_MISC_IR_CUT_CTRL_O_LEN) - 1) << MM_MISC_IR_CUT_CTRL_O_POS))
#define MM_MISC_DVP_SENSOR_PWDN          MM_MISC_DVP_SENSOR_PWDN
#define MM_MISC_DVP_SENSOR_PWDN_POS      (3U)
#define MM_MISC_DVP_SENSOR_PWDN_LEN      (1U)
#define MM_MISC_DVP_SENSOR_PWDN_MSK      (((1U << MM_MISC_DVP_SENSOR_PWDN_LEN) - 1) << MM_MISC_DVP_SENSOR_PWDN_POS)
#define MM_MISC_DVP_SENSOR_PWDN_UMSK     (~(((1U << MM_MISC_DVP_SENSOR_PWDN_LEN) - 1) << MM_MISC_DVP_SENSOR_PWDN_POS))
#define MM_MISC_DUMMY_REG                MM_MISC_DUMMY_REG
#define MM_MISC_DUMMY_REG_POS            (4U)
#define MM_MISC_DUMMY_REG_LEN            (28U)
#define MM_MISC_DUMMY_REG_MSK            (((1U << MM_MISC_DUMMY_REG_LEN) - 1) << MM_MISC_DUMMY_REG_POS)
#define MM_MISC_DUMMY_REG_UMSK           (~(((1U << MM_MISC_DUMMY_REG_LEN) - 1) << MM_MISC_DUMMY_REG_POS))

/* 0x100 : DDR_debug */
#define MM_MISC_DDR_DEBUG_OFFSET    (0x100)
#define MM_MISC_DDR_CALIB_DONE      MM_MISC_DDR_CALIB_DONE
#define MM_MISC_DDR_CALIB_DONE_POS  (0U)
#define MM_MISC_DDR_CALIB_DONE_LEN  (1U)
#define MM_MISC_DDR_CALIB_DONE_MSK  (((1U << MM_MISC_DDR_CALIB_DONE_LEN) - 1) << MM_MISC_DDR_CALIB_DONE_POS)
#define MM_MISC_DDR_CALIB_DONE_UMSK (~(((1U << MM_MISC_DDR_CALIB_DONE_LEN) - 1) << MM_MISC_DDR_CALIB_DONE_POS))

/* 0x140 : mm_berr_cfg0 */
#define MM_MISC_MM_BERR_CFG0_OFFSET      (0x140)
#define MM_MISC_REG_BERR_EN          MM_MISC_REG_BERR_EN
#define MM_MISC_REG_BERR_EN_POS      (0U)
#define MM_MISC_REG_BERR_EN_LEN      (3U)
#define MM_MISC_REG_BERR_EN_MSK      (((1U << MM_MISC_REG_BERR_EN_LEN) - 1) << MM_MISC_REG_BERR_EN_POS)
#define MM_MISC_REG_BERR_EN_UMSK     (~(((1U << MM_MISC_REG_BERR_EN_LEN) - 1) << MM_MISC_REG_BERR_EN_POS))
#define MM_MISC_REG_CODEC_BERR_EN        MM_MISC_REG_CODEC_BERR_EN
#define MM_MISC_REG_CODEC_BERR_EN_POS    (8U)
#define MM_MISC_REG_CODEC_BERR_EN_LEN    (3U)
#define MM_MISC_REG_CODEC_BERR_EN_MSK    (((1U << MM_MISC_REG_CODEC_BERR_EN_LEN) - 1) << MM_MISC_REG_CODEC_BERR_EN_POS)
#define MM_MISC_REG_CODEC_BERR_EN_UMSK   (~(((1U << MM_MISC_REG_CODEC_BERR_EN_LEN) - 1) << MM_MISC_REG_CODEC_BERR_EN_POS))
#define MM_MISC_REG_MMCPU_BERR_EN        MM_MISC_REG_MMCPU_BERR_EN
#define MM_MISC_REG_MMCPU_BERR_EN_POS    (16U)
#define MM_MISC_REG_MMCPU_BERR_EN_LEN    (1U)
#define MM_MISC_REG_MMCPU_BERR_EN_MSK    (((1U << MM_MISC_REG_MMCPU_BERR_EN_LEN) - 1) << MM_MISC_REG_MMCPU_BERR_EN_POS)
#define MM_MISC_REG_MMCPU_BERR_EN_UMSK   (~(((1U << MM_MISC_REG_MMCPU_BERR_EN_LEN) - 1) << MM_MISC_REG_MMCPU_BERR_EN_POS))
#define MM_MISC_REG_MMINFRA_BERR_EN      MM_MISC_REG_MMINFRA_BERR_EN
#define MM_MISC_REG_MMINFRA_BERR_EN_POS  (24U)
#define MM_MISC_REG_MMINFRA_BERR_EN_LEN  (5U)
#define MM_MISC_REG_MMINFRA_BERR_EN_MSK  (((1U << MM_MISC_REG_MMINFRA_BERR_EN_LEN) - 1) << MM_MISC_REG_MMINFRA_BERR_EN_POS)
#define MM_MISC_REG_MMINFRA_BERR_EN_UMSK (~(((1U << MM_MISC_REG_MMINFRA_BERR_EN_LEN) - 1) << MM_MISC_REG_MMINFRA_BERR_EN_POS))

/* 0x144 : mm_berr_cfg1 */
#define MM_MISC_MM_BERR_CFG1_OFFSET         (0x144)
#define MM_MISC_REG_BERR_CLR                MM_MISC_REG_BERR_CLR
#define MM_MISC_REG_BERR_CLR_POS            (0U)
#define MM_MISC_REG_BERR_CLR_LEN            (1U)
#define MM_MISC_REG_BERR_CLR_MSK            (((1U << MM_MISC_REG_BERR_CLR_LEN) - 1) << MM_MISC_REG_BERR_CLR_POS)
#define MM_MISC_REG_BERR_CLR_UMSK           (~(((1U << MM_MISC_REG_BERR_CLR_LEN) - 1) << MM_MISC_REG_BERR_CLR_POS))
#define MM_MISC_REG_CODEC_BERR_CLR          MM_MISC_REG_CODEC_BERR_CLR
#define MM_MISC_REG_CODEC_BERR_CLR_POS      (1U)
#define MM_MISC_REG_CODEC_BERR_CLR_LEN      (1U)
#define MM_MISC_REG_CODEC_BERR_CLR_MSK      (((1U << MM_MISC_REG_CODEC_BERR_CLR_LEN) - 1) << MM_MISC_REG_CODEC_BERR_CLR_POS)
#define MM_MISC_REG_CODEC_BERR_CLR_UMSK     (~(((1U << MM_MISC_REG_CODEC_BERR_CLR_LEN) - 1) << MM_MISC_REG_CODEC_BERR_CLR_POS))
#define MM_MISC_REG_MMCPU_BERR_CLR          MM_MISC_REG_MMCPU_BERR_CLR
#define MM_MISC_REG_MMCPU_BERR_CLR_POS      (2U)
#define MM_MISC_REG_MMCPU_BERR_CLR_LEN      (1U)
#define MM_MISC_REG_MMCPU_BERR_CLR_MSK      (((1U << MM_MISC_REG_MMCPU_BERR_CLR_LEN) - 1) << MM_MISC_REG_MMCPU_BERR_CLR_POS)
#define MM_MISC_REG_MMCPU_BERR_CLR_UMSK     (~(((1U << MM_MISC_REG_MMCPU_BERR_CLR_LEN) - 1) << MM_MISC_REG_MMCPU_BERR_CLR_POS))
#define MM_MISC_REG_MMINFRA_BERR_CLR        MM_MISC_REG_MMINFRA_BERR_CLR
#define MM_MISC_REG_MMINFRA_BERR_CLR_POS    (3U)
#define MM_MISC_REG_MMINFRA_BERR_CLR_LEN    (1U)
#define MM_MISC_REG_MMINFRA_BERR_CLR_MSK    (((1U << MM_MISC_REG_MMINFRA_BERR_CLR_LEN) - 1) << MM_MISC_REG_MMINFRA_BERR_CLR_POS)
#define MM_MISC_REG_MMINFRA_BERR_CLR_UMSK   (~(((1U << MM_MISC_REG_MMINFRA_BERR_CLR_LEN) - 1) << MM_MISC_REG_MMINFRA_BERR_CLR_POS))
#define MM_MISC_REG_BERR_LAST               MM_MISC_REG_BERR_LAST
#define MM_MISC_REG_BERR_LAST_POS           (8U)
#define MM_MISC_REG_BERR_LAST_LEN           (1U)
#define MM_MISC_REG_BERR_LAST_MSK           (((1U << MM_MISC_REG_BERR_LAST_LEN) - 1) << MM_MISC_REG_BERR_LAST_POS)
#define MM_MISC_REG_BERR_LAST_UMSK          (~(((1U << MM_MISC_REG_BERR_LAST_LEN) - 1) << MM_MISC_REG_BERR_LAST_POS))
#define MM_MISC_REG_CODEC_BERR_LAST         MM_MISC_REG_CODEC_BERR_LAST
#define MM_MISC_REG_CODEC_BERR_LAST_POS     (9U)
#define MM_MISC_REG_CODEC_BERR_LAST_LEN     (1U)
#define MM_MISC_REG_CODEC_BERR_LAST_MSK     (((1U << MM_MISC_REG_CODEC_BERR_LAST_LEN) - 1) << MM_MISC_REG_CODEC_BERR_LAST_POS)
#define MM_MISC_REG_CODEC_BERR_LAST_UMSK    (~(((1U << MM_MISC_REG_CODEC_BERR_LAST_LEN) - 1) << MM_MISC_REG_CODEC_BERR_LAST_POS))
#define MM_MISC_REG_MMCPU_BERR_LAST         MM_MISC_REG_MMCPU_BERR_LAST
#define MM_MISC_REG_MMCPU_BERR_LAST_POS     (10U)
#define MM_MISC_REG_MMCPU_BERR_LAST_LEN     (1U)
#define MM_MISC_REG_MMCPU_BERR_LAST_MSK     (((1U << MM_MISC_REG_MMCPU_BERR_LAST_LEN) - 1) << MM_MISC_REG_MMCPU_BERR_LAST_POS)
#define MM_MISC_REG_MMCPU_BERR_LAST_UMSK    (~(((1U << MM_MISC_REG_MMCPU_BERR_LAST_LEN) - 1) << MM_MISC_REG_MMCPU_BERR_LAST_POS))
#define MM_MISC_REG_MMINFRA_BERR_LAST       MM_MISC_REG_MMINFRA_BERR_LAST
#define MM_MISC_REG_MMINFRA_BERR_LAST_POS   (11U)
#define MM_MISC_REG_MMINFRA_BERR_LAST_LEN   (1U)
#define MM_MISC_REG_MMINFRA_BERR_LAST_MSK   (((1U << MM_MISC_REG_MMINFRA_BERR_LAST_LEN) - 1) << MM_MISC_REG_MMINFRA_BERR_LAST_POS)
#define MM_MISC_REG_MMINFRA_BERR_LAST_UMSK  (~(((1U << MM_MISC_REG_MMINFRA_BERR_LAST_LEN) - 1) << MM_MISC_REG_MMINFRA_BERR_LAST_POS))
#define MM_MISC_STS_BERR                    MM_MISC_STS_BERR
#define MM_MISC_STS_BERR_POS                (16U)
#define MM_MISC_STS_BERR_LEN                (1U)
#define MM_MISC_STS_BERR_MSK                (((1U << MM_MISC_STS_BERR_LEN) - 1) << MM_MISC_STS_BERR_POS)
#define MM_MISC_STS_BERR_UMSK               (~(((1U << MM_MISC_STS_BERR_LEN) - 1) << MM_MISC_STS_BERR_POS))
#define MM_MISC_STS_CODEC_BERR              MM_MISC_STS_CODEC_BERR
#define MM_MISC_STS_CODEC_BERR_POS          (17U)
#define MM_MISC_STS_CODEC_BERR_LEN          (1U)
#define MM_MISC_STS_CODEC_BERR_MSK          (((1U << MM_MISC_STS_CODEC_BERR_LEN) - 1) << MM_MISC_STS_CODEC_BERR_POS)
#define MM_MISC_STS_CODEC_BERR_UMSK         (~(((1U << MM_MISC_STS_CODEC_BERR_LEN) - 1) << MM_MISC_STS_CODEC_BERR_POS))
#define MM_MISC_STS_MMCPU_BERR              MM_MISC_STS_MMCPU_BERR
#define MM_MISC_STS_MMCPU_BERR_POS          (18U)
#define MM_MISC_STS_MMCPU_BERR_LEN          (1U)
#define MM_MISC_STS_MMCPU_BERR_MSK          (((1U << MM_MISC_STS_MMCPU_BERR_LEN) - 1) << MM_MISC_STS_MMCPU_BERR_POS)
#define MM_MISC_STS_MMCPU_BERR_UMSK         (~(((1U << MM_MISC_STS_MMCPU_BERR_LEN) - 1) << MM_MISC_STS_MMCPU_BERR_POS))
#define MM_MISC_STS_MMINFRA_BERR            MM_MISC_STS_MMINFRA_BERR
#define MM_MISC_STS_MMINFRA_BERR_POS        (19U)
#define MM_MISC_STS_MMINFRA_BERR_LEN        (1U)
#define MM_MISC_STS_MMINFRA_BERR_MSK        (((1U << MM_MISC_STS_MMINFRA_BERR_LEN) - 1) << MM_MISC_STS_MMINFRA_BERR_POS)
#define MM_MISC_STS_MMINFRA_BERR_UMSK       (~(((1U << MM_MISC_STS_MMINFRA_BERR_LEN) - 1) << MM_MISC_STS_MMINFRA_BERR_POS))
#define MM_MISC_STS_BERR_WRITE              MM_MISC_STS_BERR_WRITE
#define MM_MISC_STS_BERR_WRITE_POS          (24U)
#define MM_MISC_STS_BERR_WRITE_LEN          (1U)
#define MM_MISC_STS_BERR_WRITE_MSK          (((1U << MM_MISC_STS_BERR_WRITE_LEN) - 1) << MM_MISC_STS_BERR_WRITE_POS)
#define MM_MISC_STS_BERR_WRITE_UMSK         (~(((1U << MM_MISC_STS_BERR_WRITE_LEN) - 1) << MM_MISC_STS_BERR_WRITE_POS))
#define MM_MISC_STS_CODEC_BERR_WRITE        MM_MISC_STS_CODEC_BERR_WRITE
#define MM_MISC_STS_CODEC_BERR_WRITE_POS    (25U)
#define MM_MISC_STS_CODEC_BERR_WRITE_LEN    (1U)
#define MM_MISC_STS_CODEC_BERR_WRITE_MSK    (((1U << MM_MISC_STS_CODEC_BERR_WRITE_LEN) - 1) << MM_MISC_STS_CODEC_BERR_WRITE_POS)
#define MM_MISC_STS_CODEC_BERR_WRITE_UMSK   (~(((1U << MM_MISC_STS_CODEC_BERR_WRITE_LEN) - 1) << MM_MISC_STS_CODEC_BERR_WRITE_POS))
#define MM_MISC_STS_MMCPU_BERR_WRITE        MM_MISC_STS_MMCPU_BERR_WRITE
#define MM_MISC_STS_MMCPU_BERR_WRITE_POS    (26U)
#define MM_MISC_STS_MMCPU_BERR_WRITE_LEN    (1U)
#define MM_MISC_STS_MMCPU_BERR_WRITE_MSK    (((1U << MM_MISC_STS_MMCPU_BERR_WRITE_LEN) - 1) << MM_MISC_STS_MMCPU_BERR_WRITE_POS)
#define MM_MISC_STS_MMCPU_BERR_WRITE_UMSK   (~(((1U << MM_MISC_STS_MMCPU_BERR_WRITE_LEN) - 1) << MM_MISC_STS_MMCPU_BERR_WRITE_POS))
#define MM_MISC_STS_MMINFRA_BERR_WRITE      MM_MISC_STS_MMINFRA_BERR_WRITE
#define MM_MISC_STS_MMINFRA_BERR_WRITE_POS  (27U)
#define MM_MISC_STS_MMINFRA_BERR_WRITE_LEN  (1U)
#define MM_MISC_STS_MMINFRA_BERR_WRITE_MSK  (((1U << MM_MISC_STS_MMINFRA_BERR_WRITE_LEN) - 1) << MM_MISC_STS_MMINFRA_BERR_WRITE_POS)
#define MM_MISC_STS_MMINFRA_BERR_WRITE_UMSK (~(((1U << MM_MISC_STS_MMINFRA_BERR_WRITE_LEN) - 1) << MM_MISC_STS_MMINFRA_BERR_WRITE_POS))

/* 0x148 : mm_berr_cfg2 */
#define MM_MISC_MM_BERR_CFG2_OFFSET     (0x148)
#define MM_MISC_STS_BERR_SRC            MM_MISC_STS_BERR_SRC
#define MM_MISC_STS_BERR_SRC_POS        (0U)
#define MM_MISC_STS_BERR_SRC_LEN        (3U)
#define MM_MISC_STS_BERR_SRC_MSK        (((1U << MM_MISC_STS_BERR_SRC_LEN) - 1) << MM_MISC_STS_BERR_SRC_POS)
#define MM_MISC_STS_BERR_SRC_UMSK       (~(((1U << MM_MISC_STS_BERR_SRC_LEN) - 1) << MM_MISC_STS_BERR_SRC_POS))
#define MM_MISC_STS_BERR_ID             MM_MISC_STS_BERR_ID
#define MM_MISC_STS_BERR_ID_POS         (8U)
#define MM_MISC_STS_BERR_ID_LEN         (4U)
#define MM_MISC_STS_BERR_ID_MSK         (((1U << MM_MISC_STS_BERR_ID_LEN) - 1) << MM_MISC_STS_BERR_ID_POS)
#define MM_MISC_STS_BERR_ID_UMSK        (~(((1U << MM_MISC_STS_BERR_ID_LEN) - 1) << MM_MISC_STS_BERR_ID_POS))
#define MM_MISC_STS_CODEC_BERR_SRC      MM_MISC_STS_CODEC_BERR_SRC
#define MM_MISC_STS_CODEC_BERR_SRC_POS  (16U)
#define MM_MISC_STS_CODEC_BERR_SRC_LEN  (3U)
#define MM_MISC_STS_CODEC_BERR_SRC_MSK  (((1U << MM_MISC_STS_CODEC_BERR_SRC_LEN) - 1) << MM_MISC_STS_CODEC_BERR_SRC_POS)
#define MM_MISC_STS_CODEC_BERR_SRC_UMSK (~(((1U << MM_MISC_STS_CODEC_BERR_SRC_LEN) - 1) << MM_MISC_STS_CODEC_BERR_SRC_POS))
#define MM_MISC_STS_CODEC_BERR_ID       MM_MISC_STS_CODEC_BERR_ID
#define MM_MISC_STS_CODEC_BERR_ID_POS   (24U)
#define MM_MISC_STS_CODEC_BERR_ID_LEN   (1U)
#define MM_MISC_STS_CODEC_BERR_ID_MSK   (((1U << MM_MISC_STS_CODEC_BERR_ID_LEN) - 1) << MM_MISC_STS_CODEC_BERR_ID_POS)
#define MM_MISC_STS_CODEC_BERR_ID_UMSK  (~(((1U << MM_MISC_STS_CODEC_BERR_ID_LEN) - 1) << MM_MISC_STS_CODEC_BERR_ID_POS))

/* 0x14C : mm_berr_cfg3 */
#define MM_MISC_MM_BERR_CFG3_OFFSET       (0x14C)
#define MM_MISC_STS_MMCPU_BERR_SRC        MM_MISC_STS_MMCPU_BERR_SRC
#define MM_MISC_STS_MMCPU_BERR_SRC_POS    (0U)
#define MM_MISC_STS_MMCPU_BERR_SRC_LEN    (1U)
#define MM_MISC_STS_MMCPU_BERR_SRC_MSK    (((1U << MM_MISC_STS_MMCPU_BERR_SRC_LEN) - 1) << MM_MISC_STS_MMCPU_BERR_SRC_POS)
#define MM_MISC_STS_MMCPU_BERR_SRC_UMSK   (~(((1U << MM_MISC_STS_MMCPU_BERR_SRC_LEN) - 1) << MM_MISC_STS_MMCPU_BERR_SRC_POS))
#define MM_MISC_STS_MMCPU_BERR_ID         MM_MISC_STS_MMCPU_BERR_ID
#define MM_MISC_STS_MMCPU_BERR_ID_POS     (8U)
#define MM_MISC_STS_MMCPU_BERR_ID_LEN     (4U)
#define MM_MISC_STS_MMCPU_BERR_ID_MSK     (((1U << MM_MISC_STS_MMCPU_BERR_ID_LEN) - 1) << MM_MISC_STS_MMCPU_BERR_ID_POS)
#define MM_MISC_STS_MMCPU_BERR_ID_UMSK    (~(((1U << MM_MISC_STS_MMCPU_BERR_ID_LEN) - 1) << MM_MISC_STS_MMCPU_BERR_ID_POS))
#define MM_MISC_STS_MMINFRA_BERR_SRC      MM_MISC_STS_MMINFRA_BERR_SRC
#define MM_MISC_STS_MMINFRA_BERR_SRC_POS  (16U)
#define MM_MISC_STS_MMINFRA_BERR_SRC_LEN  (5U)
#define MM_MISC_STS_MMINFRA_BERR_SRC_MSK  (((1U << MM_MISC_STS_MMINFRA_BERR_SRC_LEN) - 1) << MM_MISC_STS_MMINFRA_BERR_SRC_POS)
#define MM_MISC_STS_MMINFRA_BERR_SRC_UMSK (~(((1U << MM_MISC_STS_MMINFRA_BERR_SRC_LEN) - 1) << MM_MISC_STS_MMINFRA_BERR_SRC_POS))
#define MM_MISC_STS_MMINFRA_BERR_ID       MM_MISC_STS_MMINFRA_BERR_ID
#define MM_MISC_STS_MMINFRA_BERR_ID_POS   (24U)
#define MM_MISC_STS_MMINFRA_BERR_ID_LEN   (6U)
#define MM_MISC_STS_MMINFRA_BERR_ID_MSK   (((1U << MM_MISC_STS_MMINFRA_BERR_ID_LEN) - 1) << MM_MISC_STS_MMINFRA_BERR_ID_POS)
#define MM_MISC_STS_MMINFRA_BERR_ID_UMSK  (~(((1U << MM_MISC_STS_MMINFRA_BERR_ID_LEN) - 1) << MM_MISC_STS_MMINFRA_BERR_ID_POS))

/* 0x150 : mm_berr_cfg4 */
#define MM_MISC_MM_BERR_CFG4_OFFSET    (0x150)
#define MM_MISC_STS_BERR_ADDR          MM_MISC_STS_BERR_ADDR
#define MM_MISC_STS_BERR_ADDR_POS      (0U)
#define MM_MISC_STS_BERR_ADDR_LEN      (32U)
#define MM_MISC_STS_BERR_ADDR_MSK      (((1U << MM_MISC_STS_BERR_ADDR_LEN) - 1) << MM_MISC_STS_BERR_ADDR_POS)
#define MM_MISC_STS_BERR_ADDR_UMSK     (~(((1U << MM_MISC_STS_BERR_ADDR_LEN) - 1) << MM_MISC_STS_BERR_ADDR_POS))

/* 0x154 : mm_berr_cfg5 */
#define MM_MISC_MM_BERR_CFG5_OFFSET      (0x154)
#define MM_MISC_STS_CODEC_BERR_ADDR      MM_MISC_STS_CODEC_BERR_ADDR
#define MM_MISC_STS_CODEC_BERR_ADDR_POS  (0U)
#define MM_MISC_STS_CODEC_BERR_ADDR_LEN  (32U)
#define MM_MISC_STS_CODEC_BERR_ADDR_MSK  (((1U << MM_MISC_STS_CODEC_BERR_ADDR_LEN) - 1) << MM_MISC_STS_CODEC_BERR_ADDR_POS)
#define MM_MISC_STS_CODEC_BERR_ADDR_UMSK (~(((1U << MM_MISC_STS_CODEC_BERR_ADDR_LEN) - 1) << MM_MISC_STS_CODEC_BERR_ADDR_POS))

/* 0x158 : mm_berr_cfg6 */
#define MM_MISC_MM_BERR_CFG6_OFFSET      (0x158)
#define MM_MISC_STS_MMCPU_BERR_ADDR      MM_MISC_STS_MMCPU_BERR_ADDR
#define MM_MISC_STS_MMCPU_BERR_ADDR_POS  (0U)
#define MM_MISC_STS_MMCPU_BERR_ADDR_LEN  (32U)
#define MM_MISC_STS_MMCPU_BERR_ADDR_MSK  (((1U << MM_MISC_STS_MMCPU_BERR_ADDR_LEN) - 1) << MM_MISC_STS_MMCPU_BERR_ADDR_POS)
#define MM_MISC_STS_MMCPU_BERR_ADDR_UMSK (~(((1U << MM_MISC_STS_MMCPU_BERR_ADDR_LEN) - 1) << MM_MISC_STS_MMCPU_BERR_ADDR_POS))

/* 0x15C : mm_berr_cfg7 */
#define MM_MISC_MM_BERR_CFG7_OFFSET        (0x15C)
#define MM_MISC_STS_MMINFRA_BERR_ADDR      MM_MISC_STS_MMINFRA_BERR_ADDR
#define MM_MISC_STS_MMINFRA_BERR_ADDR_POS  (0U)
#define MM_MISC_STS_MMINFRA_BERR_ADDR_LEN  (32U)
#define MM_MISC_STS_MMINFRA_BERR_ADDR_MSK  (((1U << MM_MISC_STS_MMINFRA_BERR_ADDR_LEN) - 1) << MM_MISC_STS_MMINFRA_BERR_ADDR_POS)
#define MM_MISC_STS_MMINFRA_BERR_ADDR_UMSK (~(((1U << MM_MISC_STS_MMINFRA_BERR_ADDR_LEN) - 1) << MM_MISC_STS_MMINFRA_BERR_ADDR_POS))

struct mm_misc_reg {
    /* 0x0 : CPU0_Boot */
    union {
        struct {
            uint32_t reg_cpu0_rvba : 32; /* [31: 0],        r/w, 0x3eff0000 */
        } BF;
        uint32_t WORD;
    } CPU0_Boot;

    /* 0x4  reserved */
    uint8_t RESERVED0x4[4];

    /* 0x8 : CPU_cfg */
    union {
        struct {
            uint32_t reg_cpu0_apb_base : 13; /* [12: 0],        r/w,       0x1c */
            uint32_t reserved_13_27    : 15; /* [27:13],       rsvd,        0x0 */
            uint32_t cpu0_ndm_rstn_en  : 1;  /* [   28],        r/w,        0x0 */
            uint32_t cpu0_hart_rstn_en : 1;  /* [   29],        r/w,        0x0 */
            uint32_t reserved_30_31    : 2;  /* [31:30],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } CPU_cfg;

    /* 0xC : CPU_sts1 */
    union {
        struct {
            uint32_t reserved_0_3         : 4;  /* [ 3: 0],       rsvd,        0x0 */
            uint32_t cpu0_lpmd_b          : 2;  /* [ 5: 4],          r,        0x0 */
            uint32_t reserved_6_15        : 10; /* [15: 6],       rsvd,        0x0 */
            uint32_t cpu0_retire_pc_39_32 : 8;  /* [23:16],          r,        0x0 */
            uint32_t cpu0_retire          : 1;  /* [   24],          r,        0x0 */
            uint32_t cpu0_pad_halted      : 1;  /* [   25],          r,        0x0 */
            uint32_t reserved_26_27       : 2;  /* [27:26],       rsvd,        0x0 */
            uint32_t cpu0_ndm_rstn_req    : 1;  /* [   28],          r,        0x0 */
            uint32_t cpu0_hart_rstn_req   : 1;  /* [   29],          r,        0x0 */
            uint32_t reserved_30_31       : 2;  /* [31:30],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } CPU_sts1;

    /* 0x10 : CPU_sts2 */
    union {
        struct {
            uint32_t cpu0_retire_pc_31_0 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } CPU_sts2;

    /* 0x14  reserved */
    uint8_t RESERVED0x14[4];

    /* 0x18 : CPU_RTC */
    union {
        struct {
            uint32_t c906_rtc_div   : 10; /* [ 9: 0],        r/w,        0xa */
            uint32_t reserved_10_29 : 20; /* [29:10],       rsvd,        0x0 */
            uint32_t c906_rtc_rst   : 1;  /* [   30],        r/w,        0x0 */
            uint32_t c906_rtc_en    : 1;  /* [   31],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } CPU_RTC;

    /* 0x1C : tzc_mmsys_misc */
    union {
        struct {
            uint32_t tzc_mm_cpu0_lock : 1;  /* [    0],          r,        0x0 */
            uint32_t reserved_1       : 1;  /* [    1],       rsvd,        0x0 */
            uint32_t tzc_mm_sram_lock : 1;  /* [    2],          r,        0x0 */
            uint32_t reserved_3_31    : 29; /* [31: 3],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } tzc_mmsys_misc;

    /* 0x20 : peri_apb_ctrl */
    union {
        struct {
            uint32_t reg_mminfra_berr_int_en : 1;  /* [    0],        r/w,        0x0 */
            uint32_t reg_berr_int_en         : 1;  /* [    1],        r/w,        0x0 */
            uint32_t reg_codec_berr_int_en   : 1;  /* [    2],        r/w,        0x0 */
            uint32_t reg_mmcpu_berr_int_en   : 1;  /* [    3],        r/w,        0x0 */
            uint32_t reserved_4_7            : 4;  /* [ 7: 4],       rsvd,        0x0 */
            uint32_t reg_mm_x2hs_sp_bypass   : 1;  /* [    8],        r/w,        0x0 */
            uint32_t reserved_9_15           : 7;  /* [15: 9],       rsvd,        0x0 */
            uint32_t rg_pclk_force_on        : 16; /* [31:16],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } peri_apb_ctrl;

    /* 0x24  reserved */
    uint8_t RESERVED0x24[8];

    /* 0x2C : mm_infra_qos_ctrl */
    union {
        struct {
            uint32_t reserved_0_1         : 2;  /* [ 1: 0],       rsvd,        0x0 */
            uint32_t reg_mmcpu0_awqos     : 1;  /* [    2],        r/w,        0x0 */
            uint32_t reg_mmcpu0_arqos     : 1;  /* [    3],        r/w,        0x0 */
            uint32_t reserved_4_15        : 12; /* [15: 4],       rsvd,        0x0 */
            uint32_t reg_h_wthre_mm2conn  : 2;  /* [17:16],        r/w,        0x0 */
            uint32_t reg_h_wthre_conn2mm  : 2;  /* [19:18],        r/w,        0x0 */
            uint32_t reg_x_wthre_mmhw2pA  : 2;  /* [21:20],        r/w,        0x0 */
            uint32_t reg_x_wthre_mmhw2ext : 2;  /* [23:22],        r/w,        0x0 */
            uint32_t reg_x_wthre_pUHS     : 2;  /* [25:24],        r/w,        0x0 */
            uint32_t reserved_26_31       : 6;  /* [31:26],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } mm_infra_qos_ctrl;

    /* 0x30  reserved */
    uint8_t RESERVED0x30[16];

    /* 0x40 : dma_clk_ctrl */
    union {
        struct {
            uint32_t dma_clk_en    : 8;  /* [ 7: 0],        r/w,       0xff */
            uint32_t reserved_8_31 : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } dma_clk_ctrl;

    /* 0x44  reserved */
    uint8_t RESERVED0x44[12];

    /* 0x50 : vram_ctrl */
    union {
        struct {
            uint32_t reg_sysram_set    : 1;  /* [    0],        w1p,        0x0 */
            uint32_t reg_h2pf_sram_rel : 2;  /* [ 2: 1],        r/w,        0x0 */
            uint32_t reserved_3        : 1;  /* [    3],       rsvd,        0x0 */
            uint32_t reg_vram_sram_rel : 1;  /* [    4],        r/w,        0x0 */
            uint32_t reserved_5        : 1;  /* [    5],       rsvd,        0x0 */
            uint32_t reg_sub_sram_rel  : 1;  /* [    6],        r/w,        0x0 */
            uint32_t reg_blai_sram_rel : 1;  /* [    7],        r/w,        0x0 */
            uint32_t reg_h2pf_sram_sel : 3;  /* [10: 8],          r,        0x0 */
            uint32_t reserved_11       : 1;  /* [   11],       rsvd,        0x0 */
            uint32_t reg_vram_sram_sel : 1;  /* [   12],          r,        0x0 */
            uint32_t reserved_13       : 1;  /* [   13],       rsvd,        0x0 */
            uint32_t reg_sub_sram_sel  : 1;  /* [   14],          r,        0x0 */
            uint32_t reg_blai_sram_sel : 1;  /* [   15],          r,        0x0 */
            uint32_t reserved_16_31    : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } vram_ctrl;

    /* 0x54  reserved */
    uint8_t RESERVED0x54[12];

    /* 0x60 : sram_parm */
    union {
        struct {
            uint32_t reg_sram_cpu_ram_dvs  : 4; /* [ 3: 0],        r/w,        0xc */
            uint32_t reg_sram_cpu_ram_dvse : 1; /* [    4],        r/w,        0x0 */
            uint32_t reg_sram_cpu_ram_nap  : 1; /* [    5],        r/w,        0x0 */
            uint32_t reserved_6_7          : 2; /* [ 7: 6],       rsvd,        0x0 */
            uint32_t reg_sram_l2ram_dvs    : 4; /* [11: 8],        r/w,        0xc */
            uint32_t reg_sram_l2ram_dvse   : 1; /* [   12],        r/w,        0x0 */
            uint32_t reg_sram_l2ram_nap    : 1; /* [   13],        r/w,        0x0 */
            uint32_t reserved_14_15        : 2; /* [15:14],       rsvd,        0x0 */
            uint32_t reg_sram_cdc_ram_dvs  : 4; /* [19:16],        r/w,        0xc */
            uint32_t reg_sram_cdc_ram_dvse : 1; /* [   20],        r/w,        0x0 */
            uint32_t reg_sram_cdc_ram_nap  : 1; /* [   21],        r/w,        0x0 */
            uint32_t reserved_22_23        : 2; /* [23:22],       rsvd,        0x0 */
            uint32_t reg_sram_sub_ram_dvs  : 4; /* [27:24],        r/w,        0xc */
            uint32_t reg_sram_sub_ram_dvse : 1; /* [   28],        r/w,        0x0 */
            uint32_t reg_sram_sub_ram_nap  : 1; /* [   29],        r/w,        0x0 */
            uint32_t reserved_30_31        : 2; /* [31:30],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } sram_parm;

    /* 0x64  reserved */
    uint8_t RESERVED0x64[60];

    /* 0xA0 : MM_INT_STA0 */
    union {
        struct {
            uint32_t mm_int_sta0 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } MM_INT_STA0;

    /* 0xA4 : MM_INT_MASK0 */
    union {
        struct {
            uint32_t mm_int_mask0 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } MM_INT_MASK0;

    /* 0xA8 : MM_INT_CLR_0 */
    union {
        struct {
            uint32_t mm_int_clr0 : 32; /* [31: 0],        w1p,        0x0 */
        } BF;
        uint32_t WORD;
    } MM_INT_CLR_0;

    /* 0xAC : MM_INT_STA1 */
    union {
        struct {
            uint32_t mm_int_sta1 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } MM_INT_STA1;

    /* 0xB0 : MM_INT_MASK1 */
    union {
        struct {
            uint32_t mm_int_mask1 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } MM_INT_MASK1;

    /* 0xB4 : MM_INT_CLR_1 */
    union {
        struct {
            uint32_t mm_int_clr1 : 32; /* [31: 0],        w1p,        0x0 */
        } BF;
        uint32_t WORD;
    } MM_INT_CLR_1;

    /* 0xb8  reserved */
    uint8_t RESERVED0xb8[56];

    /* 0xF0 : mmsys_debug_sel */
    union {
        struct {
            uint32_t mmsys_debug_sel : 4;  /* [ 3: 0],        r/w,        0x0 */
            uint32_t reserved_4_31   : 28; /* [31: 4],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } mmsys_debug_sel;

    /* 0xf4  reserved */
    uint8_t RESERVED0xf4[8];

    /* 0xFC : mmsys_misc_dummy */
    union {
        struct {
            uint32_t PIR_ctrl_o          : 1;  /* [    0],        r/w,        0x0 */
            uint32_t Light_sensor_ctrl_o : 1;  /* [    1],        r/w,        0x0 */
            uint32_t IR_cut_ctrl_o       : 1;  /* [    2],        r/w,        0x0 */
            uint32_t dvp_sensor_pwdn     : 1;  /* [    3],        r/w,        0x0 */
            uint32_t dummy_reg           : 28; /* [31: 4],        r/w,  0xfff0000 */
        } BF;
        uint32_t WORD;
    } mmsys_misc_dummy;

    /* 0x100 : DDR_debug */
    union {
        struct {
            uint32_t ddr_calib_done : 1;  /* [    0],          r,        0x0 */
            uint32_t reserved_1_31  : 31; /* [31: 1],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } DDR_debug;

    /* 0x104  reserved */
    uint8_t RESERVED0x104[60];

    /* 0x140 : mm_berr_cfg0 */
    union {
        struct {
            uint32_t reg_berr_en         : 3; /* [ 2: 0],        r/w,        0x7 */
            uint32_t reserved_3_7        : 5; /* [ 7: 3],       rsvd,        0x0 */
            uint32_t reg_codec_berr_en   : 3; /* [10: 8],        r/w,        0x7 */
            uint32_t reserved_11_15      : 5; /* [15:11],       rsvd,        0x0 */
            uint32_t reg_mmcpu_berr_en   : 1; /* [   16],        r/w,        0x1 */
            uint32_t reserved_17_23      : 7; /* [23:17],       rsvd,        0x0 */
            uint32_t reg_mminfra_berr_en : 5; /* [28:24],        r/w,       0x1f */
            uint32_t reserved_29_31      : 3; /* [31:29],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } mm_berr_cfg0;

    /* 0x144 : mm_berr_cfg1 */
    union {
        struct {
            uint32_t reg_berr_clr           : 1; /* [    0],        r/w,        0x0 */
            uint32_t reg_codec_berr_clr     : 1; /* [    1],        r/w,        0x0 */
            uint32_t reg_mmcpu_berr_clr     : 1; /* [    2],        r/w,        0x0 */
            uint32_t reg_mminfra_berr_clr   : 1; /* [    3],        r/w,        0x0 */
            uint32_t reserved_4_7           : 4; /* [ 7: 4],       rsvd,        0x0 */
            uint32_t reg_berr_last          : 1; /* [    8],        r/w,        0x0 */
            uint32_t reg_codec_berr_last    : 1; /* [    9],        r/w,        0x0 */
            uint32_t reg_mmcpu_berr_last    : 1; /* [   10],        r/w,        0x0 */
            uint32_t reg_mminfra_berr_last  : 1; /* [   11],        r/w,        0x0 */
            uint32_t reserved_12_15         : 4; /* [15:12],       rsvd,        0x0 */
            uint32_t sts_berr               : 1; /* [   16],          r,        0x0 */
            uint32_t sts_codec_berr         : 1; /* [   17],          r,        0x0 */
            uint32_t sts_mmcpu_berr         : 1; /* [   18],          r,        0x0 */
            uint32_t sts_mminfra_berr       : 1; /* [   19],          r,        0x0 */
            uint32_t reserved_20_23         : 4; /* [23:20],       rsvd,        0x0 */
            uint32_t sts_berr_write         : 1; /* [   24],          r,        0x0 */
            uint32_t sts_codec_berr_write   : 1; /* [   25],          r,        0x0 */
            uint32_t sts_mmcpu_berr_write   : 1; /* [   26],          r,        0x0 */
            uint32_t sts_mminfra_berr_write : 1; /* [   27],          r,        0x0 */
            uint32_t reserved_28_31         : 4; /* [31:28],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } mm_berr_cfg1;

    /* 0x148 : mm_berr_cfg2 */
    union {
        struct {
            uint32_t sts_berr_src       : 3; /* [ 2: 0],          r,        0x0 */
            uint32_t reserved_3_7       : 5; /* [ 7: 3],       rsvd,        0x0 */
            uint32_t sts_berr_id        : 4; /* [11: 8],          r,        0x0 */
            uint32_t reserved_12_15     : 4; /* [15:12],       rsvd,        0x0 */
            uint32_t sts_codec_berr_src : 3; /* [18:16],          r,        0x0 */
            uint32_t reserved_19_23     : 5; /* [23:19],       rsvd,        0x0 */
            uint32_t sts_codec_berr_id  : 1; /* [   24],          r,        0x0 */
            uint32_t reserved_25_31     : 7; /* [31:25],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } mm_berr_cfg2;

    /* 0x14C : mm_berr_cfg3 */
    union {
        struct {
            uint32_t sts_mmcpu_berr_src   : 1; /* [    0],          r,        0x0 */
            uint32_t reserved_1_7         : 7; /* [ 7: 1],       rsvd,        0x0 */
            uint32_t sts_mmcpu_berr_id    : 4; /* [11: 8],          r,        0x0 */
            uint32_t reserved_12_15       : 4; /* [15:12],       rsvd,        0x0 */
            uint32_t sts_mminfra_berr_src : 5; /* [20:16],          r,        0x0 */
            uint32_t reserved_21_23       : 3; /* [23:21],       rsvd,        0x0 */
            uint32_t sts_mminfra_berr_id  : 6; /* [29:24],          r,        0x0 */
            uint32_t reserved_30_31       : 2; /* [31:30],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } mm_berr_cfg3;

    /* 0x150 : mm_berr_cfg4 */
    union {
        struct {
            uint32_t sts_berr_addr : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mm_berr_cfg4;

    /* 0x154 : mm_berr_cfg5 */
    union {
        struct {
            uint32_t sts_codec_berr_addr : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mm_berr_cfg5;

    /* 0x158 : mm_berr_cfg6 */
    union {
        struct {
            uint32_t sts_mmcpu_berr_addr : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mm_berr_cfg6;

    /* 0x15C : mm_berr_cfg7 */
    union {
        struct {
            uint32_t sts_mminfra_berr_addr : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mm_berr_cfg7;
};

typedef volatile struct mm_misc_reg mm_misc_reg_t;

#endif /* __MM_MISC_REG_H__ */
